# Search Result

## 2017

## 2016

[BhJS16a] A. Bhagyanath and T. Jain and K. Schneider Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) ArchitecturesPresentation |
||||

[BhSc16a] A. Bhagyanath and K. Schneider Optimal Compilation for Exposed Datapath Architectures with Buffered Processing Units by SAT SolversPresentation |
||||

[JaSB16a] T. Jain and K. Schneider and A. Bhagyanath The Selector-Tree Network: A New Self-Routing and Nonblocking Interconnection NetworkPresentation |
||||

[JaSc16a] T. Jain and K. Schneider Verifying the Concentration Property of Permutation Networks by BDDsPresentation |
||||

[LiSc16b] X. Li and K. Schneider Control-flow Guided Clause Generation for Property Directed ReachabilityPresentation |
||||

[LiSc16d] X. Li and K. Schneider Control-flow Guided Property Directed Reachability for Synchronous ProgramsPresentation |
||||

[RBLS16a] T. Ropertz and K. Berns and X. Li and K. Schneider Verification of Behavior-Based Control Systems in their Physical EnvironmentPresentation |
||||

[RaSc16b] O. Rafique and K. Schneider Introducing MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded SystemsPresentation |
||||

[RaSc16c] O. Rafique and K. Schneider MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded SystemsPresentation |
||||

[SeSc16a] M. Senftleben and K. Schneider Specifying Weak Memory Consistency with Temporal LogicPresentation |

## 2015

## 2014

[BSBK14a] Y. Bai and K. Schneider and N. Bhardwaj and B. Katti and T. Shazadi From Clock-Driven to Data-Driven ModelsPresentation |
||||

[BSBK14b] Y. Bai and K. Schneider and N. Bhardwaj and B. Katti and T. Shazadi From Clock-Driven to Data-Driven ModelsPresentation |
||||

[BhSS14a] N. Bhardwaj and M. Senftleben and K. Schneider Abacus – A Processor Family for EducationPresentation |
||||

[BhSc14a] A. Bhagyanath and K. Schneider TTA as Predictable Architecture for Real-Time ApplicationsPresentation |
||||

[FMSS14a] F. Furbach and R. Meyer and K. Schneider and M. Senftleben Memory Model-aware Testing -- A Unified Complexity AnalysisPresentation |
||||

[GeBS14a] M. Gesell and F. Bichued and K. Schneider Using Different Representations of Synchronous Systems in SALPresentation |
||||

[KhBS14b] M.A. Ben Khadra and Y. Bai and K. Schneider Synthesis of Distributed Synchronous Specifications to SysteMoCPresentation |
||||

[LiSc14b] X. Li and K. Schneider Interactive Verification of Hybrid SystemsPresentation |
||||

[RSFB14] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira and Y. Bai Using the Base Semantics given by fUML for VerificationPresentation |
||||

[RoSF14b] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira Integrating UML Composite Structures and fUMLPresentation |
||||

[ScWi14a] K. Schneider and A. Willenbücher A New Algorithm for Carry-Free Addition of Binary Signed-Digit NumbersPresentation |

## 2013

## 2012

## 2011

## 2010

## 2009

[BaGS09c] D. Baudisch and M. Gesell and K. Schneider Online Exercise System -- A Web-Based Tool for Administration and Automatic Correction of ExercisesPresentation |