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M.Sc. Anoop Bhagyanath

email
anoop (at) rhrk.uni-kl.de
phone
+49 631 205 2811
fax
+49 631 205 4409
address
P.O. Box 3049
67653 Kaiserslautern
Germany
building/room
48/471
research interests
In real-time embedded systems, temporal correctness is as important as the logical correctness. To guarantee that all deadlines of real-time tasks will be met, it is important to estimate a safe upper bound for worst case execution time (WCET) of applications. At the same time, estimated WCET must be as close as possible to actual WCET to ensure proper hardware utilization. Conventional processor architectures employ complex features that improve the average case performance. However worst case performance is both degraded and difficult (if not impossible) to quantify. Synchronous Control Asynchronous Dataflow (SCAD) is a time-predictable or precise timed (PRET) architecture that enables safe and tight estimation of WCET of applications, which in turn guarantees temporal correctness and optimal hardware utilization respectively. My research is focused on:
  • code generation for the SCAD architecture
  • design of time-predictable features in SCAD
  • WCET analysis of SCAD programs
  • comparison of SCAD to other conventional and PRET architectures
see also my poster
publications
all | authored | edited/supervised | talks