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[Baud08] D. Baudisch Synthesis for VLIW Architectures Master Thesis |
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[DyWi08] S. Dyckmans and A. Willenbücher Design and Implementation of a Dataflow-Processor for Synchronous Programs Master Thesis |
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[Gese08] M. Gesell Probabilistic Model Checking of Synchronous Programs Master Thesis |
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[GeGe07] M. Gesell and M. Gemünde Eine Oberfläche zur Simulation synchroner Sprachen Master Thesis |
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[ScBr07] K. Schneider and J. Brandt International Conference on Theorem Proving in Higher Order Logics (TPHOL) |
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[ScBr07a] K. Schneider and J. Brandt Theorem Proving in Higher Order Logics and Applications - Emerging Trends Technical Report |
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[BrSc06] J. Brandt and K. Schneider Multimedia-Hardwareerweiterungen |
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