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[GeSD07a]
R. Gentilini and K. Schneider and A. Dreyer
Combining Interval Arithmetic and Three-Valued Temporal Logics for the Verification of Analog Systems
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
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[GeSD07b]
R. Gentilini and K. Schneider and A. Dreyer
Three-Valued Automated Reasoning on Analog Properties
Great Lakes Symposium on VLSI (GLSVLSI)
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[GeSM07]
R. Gentilini and K. Schneider and B. Mishra
Successive Abstractions of Hybrid Automata for Monotonic CTL Model Checking
International Symposium on Logical Foundations of Computer Science (LFCS)
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