Search: (more)
Header

M.tech. Tripti Jain

email
tjain25 (at) gmail.com
phone
+49 631 205 2803
fax
+49 631 205 4409
address
P.O. Box 3049
67653 Kaiserslautern
Germany
building/room
48/478
research interests
In systems-on-a-chip designs, one will soon be able to integrate really many components like processing elements and local memories with each other. To this end, one has to develop interconnection networks that make a good compromise between the chip size, the complexity of routing algorithms, and the bandwidth of the networks. Classic multistage interconnection networks like the omega-network, banyan networks, the Beneš network, and special variants like flattened banyan networks provide cost-effective solutions that still allow a high bandwidth communication. The most obvious problems of some multistage interconnection networks are either the blocking behavior of cheaper networks (a connection between two components is currently not possible because of other existing connections), and the routing problem for more expensive universal networks (like the Beneš network). My research considers new interconnection networks as well as variants of classic interconnection networks, and generally includes:
  • routing algorithms
  • interconnection networks
  • FPGA implementations
  • optimization of performance and costs (chip size)
see also my poster
publications
all | authored | edited/supervised | talks