CAD for VLSI

We tackled several important problems regarding the hierachical top-down design of very large circuits. The key aspect is Chip Planning based on an accurate area and timing estimation. A complete prototype design system, called PLAYOUT, has been developed to verify our chip planning ideas. Integrating many tools into a design environment and performing real large test designs requires research effort in the area of CAD Frameworks (design modelling, data and design management), too.

Projects

• Hierarchical Top-down Design
• PLAYOUT - A VLSI Design System
• The Chip Planner
• CAD Frameworks
• RODEO - Reuse of Design Objects

Contact

• Prof. Dr. Gerhard Zimmermann