Embedded Systems Group (ES)

Search Result

2019

BibTeX Search WWW PDF   [Jain19]
T. Jain
Nonblocking On-Chip Interconnection Networks
PhD Thesis

2018

BibTeX Search WWW PDF   [JaSc18]
T. Jain and K. Schneider
The Half Cleaner Lemma: Constructing Efficient Interconnection Networks from Sorting Networks
Parallel Processing Letters
BibTeX Search WWW PDF   [JaSc18a]
T. Jain and K. Schneider
Routing Partial Permutations in General Interconnection Networks based on Radix Sorting
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
BibTeX Search WWW PDF   [JaSc18c]
T. Jain and K. Schneider
Routing Partial Permutations in Interconnection Networks based on Radix Sorting
International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
BibTeX Search WWW PDF   [JaSc18e]
T. Jain and K. Schneider
A Recursive Concentrator Circuit and its Application as a Building Block of an Interconnection Network
BibTeX Search WWW PDF   [JaSc18f]
T. Jain and K. Schneider
Optimal Self-Routing Split Modules for Radix-based Interconnection Networks
Formal Methods and Models for Codesign (MEMOCODE)

2017

BibTeX Search WWW PDF   [DJSG17]
M. Dahlem and T. Jain and K. Schneider and M. Gillmann
Automatic Synthesis of Optimal-Size Concentrators by Answer Set Programming
Logic Programming and Nonmonotonic Reasoning (LPNMR)
BibTeX Search WWW PDF   [JaSJ17]
T. Jain and K. Schneider and A. Jain
An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip
Network on Chip Architectures (NoCArc)
BibTeX Search WWW PDF   [JaSJ17b]
T. Jain and K. Schneider and A. Jain
Deriving Concentrators from Binary Sorters Using Half Cleaners
Reconfigurable Computing and FPGAs (ReConFig)
BibTeX Search WWW PDF   [JaSJ17c]
T. Jain and K. Schneider and A. Jain
Deriving Concentrators from Binary Sorters Using Half Cleaners
BibTeX Search WWW PDF   [JaSW17]
T. Jain and K. Schneider and F. Walk
Out-of-Order Execution of Buffered Function Units in Exposed Data Path Architectures
Reconfigurable Architectures Workshop (RAW)

2016

BibTeX Search WWW PDF   [BhJS16]
A. Bhagyanath and T. Jain and K. Schneider
Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) Architectures
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
BibTeX Search WWW PDF   [JaSB16]
T. Jain and K. Schneider and A. Bhagyanath
The Selector-Tree Network: A New Self-Routing and Nonblocking Interconnection Network
International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
BibTeX Search WWW PDF   [JaSc16]
T. Jain and K. Schneider
Verifying the Concentration Property of Permutation Networks by BDDs
Formal Methods and Models for Codesign (MEMOCODE)

2015

BibTeX Search WWW PDF   [BhJS15]
A. Bhagyanath and T. Jain and K. Schneider
A Time-Predictable Model of Computation
Real-Time Systems Symposium (RTSS)

2010

BibTeX Search WWW PDF   [JBKM10]
T. Jain and P. Bansod and C.B. Singh Kushwah and M. Mewara
Reconfigurable Hardware for Median Filtering for Image Processing Applications
International Conference on Emerging Trends in Engineering and Technology (ICETET)