Embedded Systems Group (ES)

Abacus Processor Simulator

This is an instruction set simulator for the Abacus processor that has been designed in the Embedded Systems Group of the University of Kaiserslautern (more about Abacus). In the Abacus assembler program you can also specify the pipeline and the memory architecture of the computer system using the parameters shown in the example program below. If no cache should be used, specify cache size 0, and if no pipeline should be used, specify yes for SingleCycle. See also

Note that the maximal number of instructions executed by the simulator is limited to 5000 (you may contact us if you need more).