Embedded Systems Group (ES)

SCAD Processor Simulator

This is an instruction set simulator for a SCAD processor that has been designed in the Embedded Systems Group of the University of Kaiserslautern (see more details about the simulated SCAD machine below).

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The SCAD Processor

In general, SCAD (synchronous control/asynchronous data flow) processors consist of some number of processing units whose input and output ports are buffered. Each processing unit has a unique address adrU, and each one of its buffers extends this address to a unique buffer address like adrU@in0,adrU@out, or adrU@opc. Whenever a processing unit finds operands in its input buffers, it fires which means it consumes the input values and produces a specified number of copies of output values in its output buffer.

A program for a SCAD machine consists only of move instructions which move either a direct value or the result value of an output buffer to an input buffer. SCAD machines can have application-specific processing units, but the one considered here has only universal processing units with the following addresses:

Note that these addresses are used in the printout of the simulator. The behavior of these functional units are described in more detail below.

Control Unit

The control unit cu fetches move instructions from the program memory. To this end, it maintains a local program counter pc that is used to address the program memory. Whenever firing, the cu reads an instruction from ProgMem[pc] and issues it to the other processing units that add then addresses or values to their input or output buffers.

The control unit is also responsible for branch and jump instructions, i.e., conditional and unconditional branches. Unconditional branches are simply encoded as move instructions to the special address pc, i.e., $l->pc sets the pc in the control unit to l. Conditional branch instructions are handled by three lanes in the input buffer of the control unit:

As long as a pc is available locally in the cu, the corresponding move instruction is fetched and issued, and the local pc is incremented or set to l in case of an unconditional branch $l->pc. Conditional branch instructions should be implemented by the program as follows: The cu stops issuing further instructions as soon as the pc is outside the allowed addresses of the program memory. Appropriate move instructions concerning the cu are therefore the following: Note that there are no moves from the cu. Instead, the cu issues move instructions whenever it fires on the move instruction network.

Load/Store Unit

The lsu is the load/store unit of the SCAD machine with the following lanes:

Appropriate move instructions concerning the lsu are therefore the following:

Reorder Unit

If result values are not found in the desired order in the output buffers, one can make use of the reorder unit rob. The reorder unit rob has one one input lane rob@in0 and one output lane rob@out. It fires whenever there is a value in the input lane, and simply copies that value to the output lane.

Processing Units

The considered SCAD machine has universal processing units pu0,...,puN for some number N that is determined by the given SCAD program. Each processing unit puI has one input and one output buffer with the following lanes:

All processing units pu0,...,puN are capable to execute the following operations: Each puI registers the move instructions issued by the control unit whenever the address is either the source or target address of a move instruction. Moreover, result values are produced whenever input operands and opcodes are available and there is enough space in the output buffer. Finally, available result values are sent to input buffers whenever the target addresses are also available. Appropriate move instructions concerning processing units are therefore the following: